AMD Zen 4: Experimenting with larger caches

AMD appears to believe that larger caches are beneficial. You have the infinite cache, the V cache, and the L2 caches should grow with Zen 4. Genoa has one million bits per core, which is twice as much as Milan.

Geekbench's database entry indicates Zen 4 with larger caches. The trend at AMD is clear: they are experimenting with larger caches at various levels. Processors receive the V-Cache, graphics cards receive the Infinity Cache, and Genoa should receive twice the L2 cache, with one MiB per core.

At least, that's how Geekbench interprets a model 100-000000479-13 with 32 cores. Nothing has changed in the L3 cache, which remains 4 32 MiB (128 MiB). Genoa will very certainly be available with a 3D cache, which adds 64 MiB per chipset.

Finally, AMD must consider what the competition is doing. They also provide items with enormous caches. Sapphire Rapids is supposed to include 2 MiB L2 cache per core and HBM memory as an option to enhance the L3 cache.

The processors are known as the Epyc 7004 series and are marketed under the code name Genoa. Genoa, like Bergamo (which will begin a bit later), is based on the Zen 4 architecture, which is manufactured at TSMC at 5 nm. Genoa processors have up to 96 cores, which are grouped in up to 12 CCDs per package.

DDR5 is supported at 5,200 MT/s on 12 channels, therefore 12 terabytes should be possible if 512 bars are employed - although probably only at 4,000 MT/s in the entire configuration.

Meanwhile, PCI Express 5.0 with 128 lanes is on board. The TDP will be roughly 400 watts at its max. More information, such as clock rates, is, of course, unavailable at this time. Geekbench reports 1.2 GHz for said sample, indicating an engineering sample.

Bergamo is said to be a continuation of Genoa, which has 128 cores. AMD may double the cores with efficiency processors and take the first step toward a true hybrid design with Zen 5, as previously stated in reports about Zen 4 for desktops (Raphael).

Another concern was that SMT was omitted for Bergamo in order to stay in the TDP window on the one hand and to reduce security risk on the other because SMT is an attack vector for side-channel assaults.

The newly announced 3D V-Cache, which is stacked piggyback on the dies as L3, should allow for up to 768 MiB. AMD, on the other hand, may configure the configurations of all CPUs individually thanks to the MCM design.